/*
* Copyright © Shanghai Awinic Technology Co., Ltd. 2020-2020. All rights reserved.
* Description: The header file of the AFE related driver library.
* Date： 20201126
* Awinic_Version： aw_soc_driver_v1.0.0
*/
#include "compile_option.h"
#ifdef AW_86802


#ifndef __AW8680X_AFE_H
#define __AW8680X_AFE_H

/* Include ------------------------------------------------------------------*/
#include "aw8680x_def.h"

/**
  * @brief  A/D interrupt enable control enumeration definition
  */
enum afe_admcr_adie
{
	ADIE_EN = 0x02,
	ADIE_DIS = 0x00,
};
typedef enum afe_admcr_adie AFE_ADMCR_ADIE_TYPE_E;

/**
  * @brief  AFE scan mode enumeration definition
  */
enum afe_admcr_amd
{
	AMD_SINGLE_CON = 0x00U,
	AMD_SINGLE_CYCLE = 0x04U,
	AMD_FINITE_CYCLE_1 = 0x08U,
	AMD_FINITE_CYCLE_2 = 0x0CU,
	AMD_INFINITE_CYCLE = 0x10U,
	AMD_BURST_MODE = 0x14U,
};
typedef enum afe_admcr_amd AFE_ADMCR_AMD_TYPE_E;

/**
  * @brief  A/D conversion trigger source selection enumeration definition
  */
enum afe_admcr_trgs
{
	TRFS_SOFT = 0x00U,
	TRFS_TIME = 0x20U,
};
typedef enum afe_admcr_trgs AFE_ADMCR_TRGS_TYPE_E;

/**
  * @brief  Limited scan mode 1 or 2 effective conversion times enumeration definition
  */
enum afe_admcr_valid_ns
{
	VALID_NS_2 = (AW_U32)0x00000000,
	VALID_NS_4 = (AW_U32)0x00010000,
	VALID_NS_8 = (AW_U32)0x00020000,
	VALID_NS_16 = (AW_U32)0x00030000,
	VALID_NS_32 = (AW_U32)0x00040000,
	VALID_NS_64 = (AW_U32)0x00050000,
	VALID_NS_128 = (AW_U32)0x00060000,
	VALID_NS_256 = (AW_U32)0x00070000,
};
typedef enum afe_admcr_valid_ns AFE_ADMCR_VALID_NS_TYPE_E;

/**
  * @brief  Selection of operation mode in finite period scan mode enumeration definition
  */
enum afe_admcr_cal_s
{
	CALS_S_1 = (AW_U32)0x00000000, // direc averaging
	CALS_S_2 = (AW_U32)0x00080000, // remove the maximum and minimum values before averaging
};
typedef enum afe_admcr_cal_s AFE_ADMCR_CAL_S_TYPE_E;

/**
  * @brief  finite scan mode 1 or 2 invalid conversions enumeration definition
  */
enum afe_admcr_unvld_rs
{
	UNVLD_RS_0 = (AW_U32)0x00000000,
	UNVLD_RS_1 = (AW_U32)0x00100000,
	UNVLD_RS_2 = (AW_U32)0x00200000,
	UNVLD_RS_3 = (AW_U32)0x00300000,
	UNVLD_RS_4 = (AW_U32)0x00400000,
	UNVLD_RS_5 = (AW_U32)0x00500000,
	UNVLD_RS_6 = (AW_U32)0x00600000,
	UNVLD_RS_7 = (AW_U32)0x00700000,
	UNVLD_RS_8 = (AW_U32)0x00800000,
	UNVLD_RS_9 = (AW_U32)0x00900000,
	UNVLD_RS_10 = (AW_U32)0x00A00000,
	UNVLD_RS_11 = (AW_U32)0x00B00000,
	UNVLD_RS_12 = (AW_U32)0x00C00000,
	UNVLD_RS_13 = (AW_U32)0x00D00000,
	UNVLD_RS_14 = (AW_U32)0x00E00000,
	UNVLD_RS_15 = (AW_U32)0x00F00000,
};
typedef enum afe_admcr_unvld_rs AFE_ADMCR_UNVLD_RS_TYPE_E;

/**
  * @brief  CHx sensor negative input selection enumeration definition
  */
enum afe_adchcr0_pdainn
{
	PD_AINN_0 = (AW_U32)0x00000000,
	PD_AINN_1 = (AW_U32)0x00000001,
	PD_AINN_2 = (AW_U32)0x00000002,
	PD_AINN_3 = (AW_U32)0x00000003,
	PD_AINN_4 = (AW_U32)0x00000004,
	PD_AINN_5 = (AW_U32)0x00000005,
	PD_AINN_6 = (AW_U32)0x00000006,
	PD_AINN_7 = (AW_U32)0x00000007,
	PD_AINN_8 = (AW_U32)0x00000008,
	PD_AINN_9 = (AW_U32)0x00000009,
	PD_AINN_10 = (AW_U32)0x0000000A,
	PD_AINN_11 = (AW_U32)0x0000000B,
	PD_AINN_12 = (AW_U32)0x0000000C,
	PD_AINN_13 = (AW_U32)0x0000000D,
	PD_AINN_14 = (AW_U32)0x0000000E,
	PD_AINN_15 = (AW_U32)0x0000000F,
};
typedef enum afe_adchcr0_pdainn AFE_ADCHCR0_PDAINN_TYPE_E;

/**
  * @brief  CHx sensor positive input selection enumeration definition
  */
enum afe_adchcr0_pdainp
{
	PD_AINP_0 = (AW_U32)0x00000000,
	PD_AINP_1 = (AW_U32)0x00000010,
	PD_AINP_2 = (AW_U32)0x00000020,
	PD_AINP_3 = (AW_U32)0x00000030,
	PD_AINP_4 = (AW_U32)0x00000040,
	PD_AINP_5 = (AW_U32)0x00000050,
	PD_AINP_6 = (AW_U32)0x00000060,
	PD_AINP_7 = (AW_U32)0x00000070,
	PD_AINP_8 = (AW_U32)0x00000080,
	PD_AINP_9 = (AW_U32)0x00000090,
	PD_AINP_10 = (AW_U32)0x000000A0,
	PD_AINP_11 = (AW_U32)0x000000B0,
	PD_AINP_12 = (AW_U32)0x000000C0,
	PD_AINP_13 = (AW_U32)0x000000D0,
	PD_AINP_14 = (AW_U32)0x000000E0,
	PD_AINP_15 = (AW_U32)0x000000F0,
};
typedef enum afe_adchcr0_pdainp AFE_ADCHCR0_PDAINP_TYPE_E;

/**
  * @brief  PA3-PA0 analog switch control enumeration definition
  */
#define PD_SWIN_A0_DIS		((AW_U32)0x00000100)	// disable
#define PD_SWIN_A0_EN		((AW_U32)0x00000000)	// AFEa 0 strobe vs
#define PD_SWIN_A1_DIS		((AW_U32)0x00000200)	// disable
#define PD_SWIN_A1_EN		((AW_U32)0x00000000)	// AFEa 1 strobe vs
#define PD_SWIN_A2_DIS		((AW_U32)0x00000400)	// disable
#define PD_SWIN_A2_EN		((AW_U32)0x00000000)	// AFEa 2 strobe vs
#define PD_SWIN_A3_DIS		((AW_U32)0x00000800)	// disable
#define PD_SWIN_A3_EN		((AW_U32)0x00000000)	// AFEa 3 strobe vs

/**
  * @brief  ADC input working mode enumeration definition
  */
enum afe_adchcr0_endiff
{
	SINGLE_EN = (AW_U32)0x00002000,	// Single ended mode
	DOUBLE_EN = (AW_U32)0x00001000,	// Differential mode
};
typedef enum afe_adchcr0_endiff AFE_ADCHCR0_ENDIFF_TYPE_E;

/**
  * @brief  ADC input working mode enumeration definition
  */
enum afe_adchcr0_dmof
{
	/* the A/D conversion result is stored in the RSLT of the ADDRx
	register in the format of 2's original code of the conversion result */
	DMOF_0 = (AW_U32)0x00000000,

	/* the A/D conversion result is stored in the RSLT of the ADDRx
	register in the format of 2's complement of the conversion result. */
	DMOF_1 = (AW_U32)0x00004000,
};
typedef enum afe_adchcr0_dmof AFE_ADCHCR0_DMOF_TYPE_E;

/**
  * @brief  offset Residual cancellation enable signal enumeration definition
  */
enum afe_adchcr0_redos
{
	RED_OS_EN = (AW_U32)0x00008000,			// elimination of residuals
	RED_OS_DIS = (AW_U32)0x00000000,		// no elimination of residuals
};
typedef enum afe_adchcr0_redos AFE_ADCHCR0_REDOS_TYPE_E;

/**
  * @brief  Negative terminal of DC voltage channel enumeration definition
  */
enum afe_adchcr0_snmux
{
	SN_MUX_SENSOR = (AW_U32)0x00100000,	// sensor negative input channel
	SN_MUX_VTEMP = (AW_U32)0x00080000,	// vetemp input channel
	SN_MUX_VS = (AW_U32)0x00040000,		// vss input channel
	SN_MUX_GND = (AW_U32)0x00020000,	// gnd input channel
	SN_MUX_VS_2 = (AW_U32)0x00010000,	// vs/2 input channel
};
typedef enum afe_adchcr0_snmux AFE_ADCHCR0_SNMUX_TYPE_E;

/**
  * @brief  Positive terminal of DC voltage channel enumeration definition
  */
enum afe_adchcr0_spmux
{
	SP_MUX_SENSOR = (AW_U32)0x10000000,	// sensor negative input channel
	SP_MUX_VTEMP = (AW_U32)0x08000000,	// vetemp input channel
	SP_MUX_VS = (AW_U32)0x04000000,		// vss input channel
	SP_MUX_GND = (AW_U32)0x02000000,	// gnd input channel
	SP_MUX_VS_2 = (AW_U32)0x01000000,	// vs/2 input channel
};
typedef enum afe_adchcr0_spmux AFE_ADCHCR0_SPMUX_TYPE_E;

/**
  * @brief  Second level of PGA gain selection enumeration definition
  */
enum afe_adchcr1_gainpga2
{
	GAIN_PGA2_1 = (AW_U32)0x00000000,
	GAIN_PGA2_2 = (AW_U32)0x00000001,
	GAIN_PGA2_3 = (AW_U32)0x00000002,
	GAIN_PGA2_4 = (AW_U32)0x00000003,
	GAIN_PGA2_5 = (AW_U32)0x00000004,
	GAIN_PGA2_6 = (AW_U32)0x00000005,
	GAIN_PGA2_7 = (AW_U32)0x00000006,
	GAIN_PGA2_8 = (AW_U32)0x00000007,
};
typedef enum afe_adchcr1_gainpga2 AFE_ADCHCR1_GAINPGA2_TYPE_E;

/**
  * @brief  First level of PGA gain selection enumeration definition
  */
enum afe_adchcr1_gainpga1
{
	GAIN_PGA1_1 = (AW_U32)0x00000000,
	GAIN_PGA1_16 = (AW_U32)0x00000010,
	GAIN_PGA1_32 = (AW_U32)0x00000020,
	GAIN_PGA1_64 = (AW_U32)0x00000030,
	GAIN_PGA1_128 = (AW_U32)0x00000040,
};
typedef enum afe_adchcr1_gainpga1 AFE_ADCHCR1_GAINPGA1_TYPE_S;

/**
  * @brief  PGA2 filter enable control bit enumeration definition
  */
enum afe_adchcr1_pdfilter
{
	PD_FILTER_EN = (AW_U32)0x00000000,	// turn on
	PD_FILTER_DIS = (AW_U32)0x00000100,	// turn off
};
typedef enum afe_adchcr1_pdfilter AFE_ADCHCR1_PDFILTER_TYPE_S;

/**
  * @brief  PGA2 enable control bit enumeration definition
  */
enum afe_adchcr1_pdpga2
{
	PD_PGA2_EN = (AW_U32)0x00000000,	// enable pga2
	PD_PGA2_DIS = (AW_U32)0x00000200,	// disable pga2
};
typedef enum afe_adchcr1_pdpga2 AFE_ADCHCR1_PDPGA2_TYPE_E;

/**
  * @brief  PGA2 enable control bit enumeration definition
  */
enum afe_adchcr1_pdpga1
{
	PD_PGA1_EN = (AW_U32)0x00000000,	// enable pga2
	PD_PGA1_DIS = (AW_U32)0x00000400,	// disable pga2
};
typedef enum afe_adchcr1_pdpga1 AFE_ADCHCR1_PDPGA1_TYPE_E;

/**
  * @brief  PGA enable control bit enumeration definition
  */
enum afe_adchcr1_enpga
{
	PGA_EN = (AW_U32)0x00000800,	// enable pga2
	PGA_DIS = (AW_U32)0x00000000,	// disable pga2
};
typedef enum afe_adchcr1_enpga AFE_ADCHCR1_ENPGA_TYPE_E;

/**
  * @brief  SAR ADC output flip enable enumeration definition
  */
enum afe_adchcr1_invad
{
	INV_AD_EN = (AW_U32)0x00001000,		// flip
	INV_AD_DIS = (AW_U32)0x00000000,	// no flip
};
typedef enum afe_adchcr1_invad AFE_ADCHCR1_INVAD_TYPE_E;

/**
  * @brief  ADC BIAS current control enumeration definition
  */
enum afe_adchcr1_adcibias
{
	ADC_IBIAS_0 = (AW_U32)0x00000000,	// 2uA
	ADC_IBIAS_1 = (AW_U32)0x00010000,	// 2.5uA
	ADC_IBIAS_2 = (AW_U32)0x00020000,	// 3uA
	ADC_IBIAS_3 = (AW_U32)0x00030000,	// 3.5uA
	ADC_IBIAS_4 = (AW_U32)0x00040000,	// 4uA
	ADC_IBIAS_5 = (AW_U32)0x00050000,	// 4.5uA
	ADC_IBIAS_6 = (AW_U32)0x00060000,	// 5uA
	ADC_IBIAS_7 = (AW_U32)0x00070000,	// 5.5uA
};
typedef enum afe_adchcr1_adcibias AFE_ADCHCR1_ADCIBIAS_TYPE_E;

/**
  * @brief  PGA output common mode voltage selection enumeration definition
  */
enum afe_adchcr1_vcmadj
{
	VCM_ADJ_0 = (AW_U32)0x00000000,	// 0: 0.5*AVDD
	VCM_ADJ_1 = (AW_U32)0x00100000,	// 1: 0.5*AVDD - 1
};
typedef enum afe_adchcr1_vcmadj AFE_ADCHCR1_VCMADJ_TYPE_E;

/**
  * @brief  ADC refrence voltage selection enumeration definition
  */
enum afe_adchcr1_vref_gen_sel
{
	VREF_GEN_SEL_VDD = (AW_U32)0x00000000,	// selection VDD
	VREF_GEN_SEL_VRP = (AW_U32)0x00200000,	// selection VRP
};
typedef enum afe_adchcr1_vref_gen_sel AFE_ADCHCR1_VREF_GEN_SEL_TYPE_E;

/**
  * @brief  VRP voltage selection enumeration definition
  */
enum afe_adchcr1_vref_sel
{
	VREF_SEL_0 = (AW_U32)0x00000000,	// selection 2.4V
	VREF_SEL_1 = (AW_U32)0x00400000,	// selection 2.8V
	VREF_SEL_2 = (AW_U32)0x00800000,	// selection 3.0V
	VREF_SEL_3 = (AW_U32)0x00C00000,	// selection 3.1V
};
typedef enum afe_adchcr1_vref_sel AFE_ADCHCR1_VREF_SEL_TYPE_E;

/**
  * @brief  PGA RC filter output frequency selection enumeration definition
  */
enum afe_adchcr1_bm_filter
{
	BW_FILTER_0 = (AW_U32)0x00000000,	// selection 125kHz
	BW_FILTER_1 = (AW_U32)0x01000000,	// selection 250kHz
	BW_FILTER_2 = (AW_U32)0x02000000,	// selection 167kHz
	BW_FILTER_3 = (AW_U32)0x03000000,	// selection 500kHz
	BW_FILTER_4 = (AW_U32)0x04000000,	// selection 143kHz
	BW_FILTER_5 = (AW_U32)0x05000000,	// selection 333kHz
	BW_FILTER_6 = (AW_U32)0x06000000,	// selection 200kHz
	BW_FILTER_7 = (AW_U32)0x07000000,	// selection 1000kHz
};
typedef enum afe_adchcr1_bm_filter AFE_ADCHCR1_BW_FILTER_TYPE_E;

/**
  * @brief  PGA module overall current selection enumeration definition
  */
enum afe_adchcr1_pga_ibiase
{
	PGA_IBIASE_0 = (AW_U32)0x00000000,	// selection 1uA
	PGA_IBIASE_1 = (AW_U32)0x10000000,	// selection 1.25uA
	PGA_IBIASE_2 = (AW_U32)0x20000000,	// selection 1.5uA
	PGA_IBIASE_3 = (AW_U32)0x30000000,	// selection 1.75uA
	PGA_IBIASE_4 = (AW_U32)0x40000000,	// selection 2uA
	PGA_IBIASE_5 = (AW_U32)0x50000000,	// selection 2.25uA
	PGA_IBIASE_6 = (AW_U32)0x60000000,	// selection 2.5uA
	PGA_IBIASE_7 = (AW_U32)0x70000000,	// selection 2.75uA
};
typedef enum afe_adchcr1_pga_ibiase AFE_ADCHCR1_PGA_IBIASE_TYPE_E;

/**
  * @brief  DAC calibration offset range enumeration definition
  */
enum afe_dachcr_vdac_range
{
	VDAC_RANGE_0 = (AW_U32)0x00000000,	// 0.540*VS/3
	VDAC_RANGE_1 = (AW_U32)0x00000001,	// 0.540*VS/4
	VDAC_RANGE_2 = (AW_U32)0x00000002,	// 0.540*VS/5
	VDAC_RANGE_3 = (AW_U32)0x00000003,	// 0.540*VS/6
};
typedef enum afe_dachcr_vdac_range AFE_DACHCR_VDAC_RANGE_TYPE_E;

/**
  * @brief  DAC direction select enumeration definition
  */
enum afe_dachcr_dir_sel
{
	DIR_MODE1 = (AW_U32)0x00000100,	// MODE1
	DIR_MODE0 = (AW_U32)0x00000200,	// MODE0
	DIR_DAC = (AW_U32)0x00000400,	// DAC
};
typedef enum afe_dachcr_dir_sel AFE_DACHCR_DIR_SEL_TYPE_E;

/**
  * @brief  turn on DAC negative current input enumeration definition
  */
enum afe_dachcr_dac_vin_enum
{
	DAC_VIN_EN = (AW_U32)0x00000800,	// dac vin turn on
	DAC_VIN_DIS = (AW_U32)0x00000000,	// dac vin turn off
};
typedef enum afe_dachcr_dac_vin_enum AFE_DACHCR_DAC_VIN_TYPE_E;

/**
  * @brief  enable calibration offset DAC enumeration definition
  */
enum afe_dachcr_en_dac
{
	DAC_OFFSET_EN = (AW_U32)0x00001000,		// enable dac offset
	DAC_OFFSET_DIS = (AW_U32)0x00000000,	// disable dac offset
};
typedef enum afe_dachcr_en_dac AFE_DACHCR_EN_DAC_TYPE_E;

/**
  * @brief  enable digital DAC calibration loop operation enumeration definition
  */
enum afe_dachcr_en_dac_cal
{
	EN_DAC_CAL_EN = (AW_U32)0x00002000,
	EN_DAC_CAL_DIS = (AW_U32)0x00000000,
};
typedef enum afe_dachcr_en_dac_cal AFE_DACHCR_EN_DAC_CAL_TYPE_E;

/**
  * @brief adc channel enumeration definition
  */
#define ADC_CHANNEL_0		((AW_U32)0x00000001)
#define ADC_CHANNEL_1		((AW_U32)0x00000002)
#define ADC_CHANNEL_2		((AW_U32)0x00000004)
#define ADC_CHANNEL_3		((AW_U32)0x00000008)
#define ADC_CHANNEL_4		((AW_U32)0x00000010)
#define ADC_CHANNEL_5		((AW_U32)0x00000020)
#define ADC_CHANNEL_6		((AW_U32)0x00000040)
#define ADC_CHANNEL_7		((AW_U32)0x00000080)
#define ADC_CHANNEL_8		((AW_U32)0x00000100)
#define ADC_CHANNEL_9		((AW_U32)0x00000200)
#define ADC_CHANNEL_10		((AW_U32)0x00000400)
#define ADC_CHANNEL_11		((AW_U32)0x00000800)
#define ADC_CHANNEL_12		((AW_U32)0x00001000)
#define ADC_CHANNEL_13		((AW_U32)0x00002000)
#define ADC_CHANNEL_14		((AW_U32)0x00004000)
#define ADC_CHANNEL_15		((AW_U32)0x00008000)

/**
 * @brief  ADC CLK Configuration Structure definition
**/
#define ADC_CLK_10KHZ		((AW_U32)60)
#define ADC_CLK_60KHZ		((AW_U32)0x0A)
#define ADC_CLK_100KHZ		((AW_U32)0x06)

/**
 * @brief  AFE ADCH_CR0 Initialization Configuration Structure definition
**/
struct adch_cr0_init_struct {
	AFE_ADCHCR0_PDAINN_TYPE_E		pd_ainn_e;	// CHx sensor negative input selection enumeration definition
	AFE_ADCHCR0_PDAINP_TYPE_E		pd_ainp_e;	// CHx sensor positive input selection enumeration definition
	AW_U32							pd_swin_e;	// PA3-PA0 analog switch control enumeration definition
	AFE_ADCHCR0_ENDIFF_TYPE_E		en_diff_e;	// ADC input working mode enumeration definition
	AFE_ADCHCR0_DMOF_TYPE_E			dmof_e;		// ADC input working mode enumeration definition
	AFE_ADCHCR0_REDOS_TYPE_E		red_os_e;	// offset Residual cancellation enable signal
	AFE_ADCHCR0_SNMUX_TYPE_E		sn_mux_e;	// Nositive terminal of DC voltage channel.
	AFE_ADCHCR0_SPMUX_TYPE_E		sp_mux_e;	// Positive terminal of DC voltage channel.
};
typedef struct adch_cr0_init_struct AFE_ADCH_CR0_INIT_TYPE_S;

/**
 * @brief  AFE ADCH_CR1 Initialization Configuration Structure definition
**/
struct adch_cr1_init_struct {
	AFE_ADCHCR1_GAINPGA2_TYPE_E			gain_pga2_e;	// Second level of PGA gain selection
	AFE_ADCHCR1_GAINPGA1_TYPE_S			gain_pga1_e;	// First level of PGA gain selection
	AFE_ADCHCR1_PDFILTER_TYPE_S			pd_filter_e;	// PGA2 filter enable control bit
	AFE_ADCHCR1_PDPGA2_TYPE_E			pd_pga2_e;		// PGA2 enable control bit
	AFE_ADCHCR1_PDPGA1_TYPE_E			pd_pga1_e;		// PGA enable control bit
	AFE_ADCHCR1_ENPGA_TYPE_E			en_pga_e;		// PGA enable control bit
	AFE_ADCHCR1_INVAD_TYPE_E			inv_ad_e;		// SAR ADC output flip enable
	AFE_ADCHCR1_ADCIBIAS_TYPE_E			adc_ibias_e;	// ADC BIAS current control
	AFE_ADCHCR1_VCMADJ_TYPE_E			vcm_adj_e;		// PGA output common mode voltage selection
	AFE_ADCHCR1_VREF_GEN_SEL_TYPE_E		vref_gen_sel_e;	// ADC voltage selection
	AFE_ADCHCR1_VREF_SEL_TYPE_E			vref_sel_e;		// VRP voltage selection
	AFE_ADCHCR1_BW_FILTER_TYPE_E		bw_filter_e;	// PGA RC filter output frequency selection
	AFE_ADCHCR1_PGA_IBIASE_TYPE_E		pga_ibiase_e;	// PGA module overall current selection
};
typedef struct adch_cr1_init_struct AFE_ADCH_CR1_INIT_TYPE_S;

/**
 * @brief DAC CR Initialization Configuration Structure definition
**/
struct dach_cr_init_struct {
	AFE_DACHCR_VDAC_RANGE_TYPE_E		vdac_range_e;	// DAC calibration offset range
	AFE_DACHCR_DIR_SEL_TYPE_E			dir_sel_e;		// DAC direction select
	AFE_DACHCR_DAC_VIN_TYPE_E			dac_vin_e;		// turn on DAC negative current input
	AFE_DACHCR_EN_DAC_TYPE_E			en_dac_e;		// enable calibration offset DAC
	AFE_DACHCR_EN_DAC_CAL_TYPE_E		en_dac_cal_e;	// enable digital DAC calibration loop operation
};
typedef struct dach_cr_init_struct DACH_CR_INIT_TYPE_S;

/**
 * @brief  AFE ADMCR Initialization Configuration Structure definition
**/
struct admcr_init_struct {
	AFE_ADMCR_ADIE_TYPE_E			admcr_adie_e;		// A/D interrupt enable control enumeration definition
	AFE_ADMCR_AMD_TYPE_E			admcr_amd_e;		// AFE scan mode enumeration definition
	AFE_ADMCR_TRGS_TYPE_E			admcr_trgs_e;		// A/D conversion trigger source selection enumeration definition
	AFE_ADMCR_VALID_NS_TYPE_E		admcr_valid_ns_e;	// Limited scan mode 1 or 2 effective conversion times enumeration definition
	AFE_ADMCR_CAL_S_TYPE_E			admcr_cal_s_e;
	AFE_ADMCR_UNVLD_RS_TYPE_E		admcr_unvld_rs_e;	// finite scan mode 1 or 2 invalid conversions enumeration definition
};
typedef struct admcr_init_struct AFE_ADMCR_INIT_TYPE_S;

/**
 * @brief  AFE Initialization Configuration Structure definition
**/
struct afe_init_struct {
	AFE_ADCH_CR0_INIT_TYPE_S		afe_adch_cr0_s[16];
	AFE_ADCH_CR1_INIT_TYPE_S		afe_adch_cr1_s[16];
	DACH_CR_INIT_TYPE_S				dac_cr_s[16];
	AFE_ADMCR_INIT_TYPE_S			afe_admcr_s;
};
typedef struct afe_init_struct AFE_INIT_TYPE_S;

/**
 * @brief  AFE Configuration Structure definition
**/
struct afe_handle_struct {
	AW_U32 adc_channel;				// AFE channel sel
	AW_U32 adc_clkdiv;				// ADC clkdiv sel
	IRQ_PRI_E afe_irq_pri_e;		// AFE irq priority
	AFE_INIT_TYPE_S init_s;			// AFE communication parameters
};
typedef struct afe_handle_struct AFE_HANDLE_TYPE_S;

#define ADC_CHANNEL				(16U)					// adc channel total number
#define ADMCR_ADST_EN			((AW_U32)0x00000800)	// A/D conversion begins.
#define ADMCR_ADST_DIS			(~ADMCR_ADST_EN)		// A/D conversion stop.
#define ADMCE_ADC_EN			((AW_U32)0x01)
#define ADMCE_ADC_DIS			(~ADMCE_ADC_EN)
#define ADSR_ADF				((AW_U32)0x00000001)	// write 1 to clear this flag.
#define ADSR_BUSY				((AW_U32)0x08)			// afe busy control bit.

#define AFE_TIMEOUT				(11500)		// Timeout judgment 10ms.
#define ADC_THRESHOLD			(0x2000)	// 14-bit ADC, the most significant sign bit.

#ifdef AFE_TEST
	extern AW_U16 g_afe_buff[ADC_CHANNEL];	// g_afe_buff
	#define AFE_BUFF_LEN	(4U)
#endif

#define ADC_SOFT_GO()			(AFE->ADMCR |= ADMCR_ADST_EN)
#define ADC_SOFT_STOP()			(AFE->ADMCR &= ADMCR_ADST_DIS)
#define AFE_CLEAN_STA()			(AFE->ADSR |= ADSR_ADF)

RET_STATUS_E afe_init(AFE_HANDLE_TYPE_S *p_afe_lib);
RET_STATUS_E afe_wait_free(void);
RET_STATUS_E afe_wait_end(void);
void afe_irq(void);

#endif
#endif
